#!/bin/sh
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# Clean up the results directory
rm -rf results
mkdir results

#Synthesize the Wrapper Files

echo 'Synthesizing example design with Synplify'
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx


# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../axi64_8k_2clk_fifo.ngc results/

#  Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/axi64_8k_2clk_fifo_exdes.ucf results/

cd results

echo 'Running ngdbuild'

ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi64_8k_2clk_fifo_exdes

echo 'Running map'
map axi64_8k_2clk_fifo_exdes -o mapped.ncd

echo 'Running par'
par mapped.ncd routed.ncd

echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow

echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm axi64_8k_2clk_fifo_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v

