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echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogcomp -work work ..\\..\\implement\\results\\routed.v

echo "Compiling Test Bench Files"
vhpcomp -work work ..\\input_sample_fifo_pkg.vhd
vhpcomp -work work ..\\input_sample_fifo_rng.vhd 
vhpcomp -work work ..\\input_sample_fifo_dgen.vhd
vhpcomp -work work ..\\input_sample_fifo_dverif.vhd
vhpcomp -work work ..\\input_sample_fifo_pctrl.vhd 
vhpcomp -work work ..\\input_sample_fifo_synth.vhd 
vhpcomp -work work ..\\input_sample_fifo_tb.vhd

fuse work.input_sample_fifo_tb work.glbl -L simprims_ver -o input_sample_fifo_tb.exe

.\\input_sample_fifo_tb.exe -sdfmax /input_sample_fifo_tb/input_sample_fifo_synth_inst/input_sample_fifo_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl
