                                                          Log file                                                       

Generated by MIG MIG Version 1.8
Coregen 14.4 - Build Number P.49d on Thu Jan 17 10:44:37 2013


Creating the directory /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_designCreated the UCF file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/constraints/ddr3_interface_fast.ucf Successfully
Created the SDC file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/constraints/ddr3_interface_fast.xdc SuccessfullyCreated the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_common.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_col_mach.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_top.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v Successfully
 ..Successful
Created the file - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/../docs/phy_only_support_readme.txt Successfully
 ..SuccessfulCreated the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.vCreated the Top Level File - /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast.veoThe design output files are located in /home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/tmp/_cg/ddr3_interface_fast/user_design/rtl and ..user_design/constraints for rtl & ucf files respectively.