--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
-- 
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--------------------------------------------------------------------------------
--
-- Filename: input_sample_fifo_exdes.vhd
--
-- Description:
--   This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity input_sample_fifo_exdes is
   PORT (
           WR_CLK                    : IN  std_logic;
     	   RD_CLK                    : IN  std_logic;
           ALMOST_EMPTY              : OUT std_logic;
           RST                       : IN  std_logic;
           WR_EN 		     : IN  std_logic;
           RD_EN                     : IN  std_logic;
           DIN                       : IN  std_logic_vector(28-1 DOWNTO 0);
           DOUT                      : OUT std_logic_vector(28-1 DOWNTO 0);
           FULL                      : OUT std_logic;
           EMPTY                     : OUT std_logic);

end input_sample_fifo_exdes;



architecture xilinx of input_sample_fifo_exdes is

  signal wr_clk_i : std_logic;
  signal rd_clk_i : std_logic;



  component input_sample_fifo is
   PORT (
           WR_CLK                    : IN  std_logic;
     	   RD_CLK                    : IN  std_logic;
           ALMOST_EMPTY              : OUT std_logic;
           RST                       : IN  std_logic;
           WR_EN 		     : IN  std_logic;
           RD_EN                     : IN  std_logic;
           DIN                       : IN  std_logic_vector(28-1 DOWNTO 0);
           DOUT                      : OUT std_logic_vector(28-1 DOWNTO 0);
           FULL                      : OUT std_logic;
           EMPTY                     : OUT std_logic);

  end component;


begin

  wr_clk_buf: bufg
    PORT map(
      i => WR_CLK,
      o => wr_clk_i
      );

  rd_clk_buf: bufg
    PORT map(
      i => RD_CLK,
      o => rd_clk_i
      );


  exdes_inst : input_sample_fifo 
    PORT MAP (
           WR_CLK                    => wr_clk_i,
           RD_CLK                    => rd_clk_i,
           ALMOST_EMPTY              => almost_empty,
           RST                       => rst,
           WR_EN 		     => wr_en,
           RD_EN                     => rd_en,
           DIN                       => din,
           DOUT                      => dout,
           FULL                      => full,
           EMPTY                     => empty);

end xilinx;
