The following files were generated for 'ddr_vio_sync_async_out72' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/par/

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * ddr_vio_sync_async_out72.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * ddr_vio_sync_async_out72.cdc
   * ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.ucf
   * ddr_vio_sync_async_out72.constraints/ddr_vio_sync_async_out72.xdc
   * ddr_vio_sync_async_out72.ngc
   * ddr_vio_sync_async_out72.ucf
   * ddr_vio_sync_async_out72.xdc
   * ddr_vio_sync_async_out72_xmdf.tcl

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * ddr_vio_sync_async_out72.asy

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * ddr_vio_sync_async_out72.gise
   * ddr_vio_sync_async_out72.xise

Deliver Readme:
   Readme file for the IP.

   * ddr_vio_sync_async_out72_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * ddr_vio_sync_async_out72_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

