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UHD - USRP-B100 Series Device Manual
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.. contents:: Table of Contents

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Comparative features list
------------------------------------------------------------------------

**Hardware Capabilities:**
 * 1 transceiver card slot
 * External PPS reference input
 * External 10 MHz reference input
 * Configurable clock rate (defaults 64 MHz)

**FPGA Capabilities:**
 * 1 RX DDC chain in FPGA
 * 1 TX DUC chain in FPGA
 * Timed commands in FPGA
 * Timed sampling in FPGA
 * sc8 and sc16 sample modes

   * Up to 8 MHz of RF BW with 16-bit samples
   * Up to 16 MHz of RF BW with 8-bit samples

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Specify a Non-standard Image
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UHD software will automatically select the USRP B100 images from the installed images package.
The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters.

Example device address string representations to specify non-standard images:

::

    fpga=usrp_b100_fpga_2rx.bin

    -- OR --

    fw=usrp_b100_fw.ihx

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Changing the Master Clock Rate
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The master clock rate of the B100 feeds both the FPGA DSP and the codec chip.
Hundreds of rates between 32 MHz and 64 MHz are available.
A few notable rates are:

* **64 MHz:** maximum rate of the codec chip
* **61.44 MHz:** good for UMTS/WCDMA applications
* **52 MHz:** good for GSM applications

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Set 61.44 MHz - uses external VCXO
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To use the 61.44 MHz clock rate, the USRP embedded will require one jumper to be moved,
and X4 must be populated with a 61.44 MHz oscillator.

* **J15** is a three pin header, move the jumper to (pin1, pin2)
* **357LB3I061M4400** is the recommended oscillator for X4

**Note:** See instructions below to communicate the desired clock rate into UHD software.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Set other rates - uses internal VCO
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
To use other clock rates, the jumper will need to be in the default position.

* **J15** is a three pin header, move the jumper to (pin2, pin3)

To communicate the desired clock rate into UHD software,
specify the special device address argument,
where the key is **master_clock_rate** and the value is a rate in Hz.
Example:
::

    uhd_usrp_probe --args="master_clock_rate=52e6"

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Hardware setup notes
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Front panel LEDs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The LEDs on the front panel can be useful in debugging hardware and software issues.
The LEDs reveal the following about the state of the device:

* **LED A:** transmitting
* **LED B:** FPGA loaded
* **LED C:** receiving
* **LED D:** FPGA loaded
* **LED E:** reference lock
* **LED F:** board power

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Miscellaneous
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Available Sensors
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The following sensors are available;
they can be queried through the API.

* **ref_locked:** clock reference locked (internal/external)
